Novel Flip-flop Designs Tolerant to Soft-errors and Crosstalk Effects

OF THE THESIS Novel Flip-Flop Designs Tolerant to Soft-Errors and Crosstalk Effects by Aditya Jagirdar Thesis Director: Prof. Michael L. Bushnell The desire to make technology faster, smaller and more affordable compels us to shrink transistors further. As we realize designs with millions of transistors, most of the existing problems increase in severity and newer problems crop up. One major new problem is Soft-Errors in logic and the result is a severe decrease in circuit reliability. This problem has been common in static memories since 1970 and, hence, faulttolerant memory techniques are well developed. However, soft-errors today affect sequential logic as well. Interconnect crosstalk gets severe as we move towards higher operational frequencies and must be dealt in conjunction with soft-errors. In this work, we propose novel flip-flop designs, which, unlike previous designs, are immune to soft-errors and crosstalk effects during the entire Window of Vulnerability (WoV), even around the clock edge. The Crosstalk and Soft-Error Tolerant Flip-Flop (XSEUFF2) can recover from transient pulses generated in the combinational logic and on internal nodes of the master and slave latches. It is also tolerant to any signal delays arising due to crosstalk. The area, timing and power overheads of this design over Mitra’s Basic Scan Flip-Flop (BSFF) are 37%, 30% and 250% while those of Mitra’s Error Blocking Scan Flip-Flop (EBSFF) and Error Trapping Scan Flip-Flop